Intel Goes 3-D On Transistor Design Concept

In the three-dimensional tri-gate transistor, there's a lot of gate surface area in contact with the semiconductor material, so there's a lot more of the tiny strip of semiconductor material (pictured as the blue inversion layer) for current to flow through. This makes the difference between the transistor's "on" and "off" states much larger, which means that the transistor can switch between states much faster while still producing a clear string of ons and offs. Image Credit: Intel

Intel Goes 3-D On Transistor Design Concept

This month will go down in electronics history as the time marked as the advent of transistor design going three dimensional (3-D).

Intel has been exploring this new 22nm "tri-gate" transistor for over a decade, and the company first announced a significant breakthrough with the design in 2002. A trickle of announcements followed over the years, as the new transistor progressed from being one possible direction among many to its newly crowned status as the official future of Intel's entire product line.

This approach is significant primarily because it improves the core function of a computer to process data via the transistor switch. The transistor's substrate is sort of like a magic wire that can either conduct electricity or not, and the gate is the switch that controls whether the wire will conduct or not.

When a voltage is applied to the metal plate that forms the transistor's gate, a tiny strip of semiconductor material between the source and the drain changes from an insulator into a conductor, thereby turning the switch "on" and allowing current to flow from the source to the drain. When the voltage is removed, current stops flowing ... or, at least, current is supposed to stop flowing when the switch is off. In reality, trace amounts of current will constantly flow between the source and the drain. This so-called "leakage current" wastes precious power and becomes even more of a problem as transistors get smaller and more numerous.

Standard transistor gate design (note: blue layer functions as the switch). Image Credit: Intel

In the three-dimensional tri-gate transistor, there's a lot of gate surface area in contact with the semiconductor material, so there's a lot more of the tiny strip of (magic wire) semiconductor material (pictured as the blue inversion layer) for current to flow through. This makes the difference between the transistor's "on" and "off" states much larger, which means that the transistor can switch between states much faster while still producing a clear string of ons and offs.

Planar transistor vs Tri-Gate transistor. Image Credit: Intel

Another advantage relates to reducing its power consumption. One could take advantage of this new structure by applying less voltage to the gate. Sure, the blue inversion layer adjacent to the gate would be less conductive, but there's more of it available to carry electrons, so one can still let the same amount of current through when the switch is on.

The middle part that sticks up there is called a "fin." If Intel wants to stretch the gate and inversion layer sizes out even further, its approach lets it add multiple fins under a single gate, for boosts in performance and/or power at the expense of transistor density.

Ultimately, the advantage of stretching the gate out into the third dimension are that one can much more easily either boost the chip's frequency or reduce its power, or some mix of the two.

Graph shows advantages of new 22nm 3-D design over 32nm Standard gate design in transistors. Image Credit: Intel

Intel claims that the 22nm tri-gate transistors switch between 18 and 37 percent faster than the 32nm planar type (depending on the voltage level). Or, looked at from the voltage side, the new design can reduce active power by up to 50 percent.

These design advantages deliver very significant jumps in performance and efficiency, and these 3-D transistors will go a long way toward making Intel's "x86 in smartphones at 22nm" dreams come true.
(ht: Ars Technica)

Additional resource reading

• Intel's tri-gate page (intel.com)
• A tri-gate press briefing from 2006 (download.intel.com)
• Another good Intel tri-gate explainer (intel.com)
• Intel press backgrounder on tri-gate. (newsroom.intel.com)
• Intel's announcement (newsroom.intel.com)
• RWT on challenges at 22nm (realworldtech.com)